1. Field of the Invention
The present invention relates to a data processing apparatus for binarizing input data based on a threshold voltage.
2. Description of the Related Art
Electronic devices of recent years have been required to transmit a large volume of data between the devices, boards on which IC chips are mounted, and the IC chips at a high speed, so that a frequency of a transmission clock used for data transmission has been steadily increased. When the frequency of the transmission clock has been increased in this manner, jitter tolerance of the transmission clock relative to transmission data is reduced and reception data obtained upon receiving transmission data is subject to degradation. Further, because of the degradation of the reception data, a transmission error is generated. Thus, preferably, the transmission clock is in precise synchronization with the transmission data.
For example, FIG. 1 is a diagram showing an example of a duty cycle of the reception data varied due to the degradation of the reception data. In the example shown in FIG. 1, synchronization with the reception data is detected at a falling edge of a synchronous clock and the reception data is captured at a rising edge of the synchronous clock. In this case, when the duty cycle of the reception data is varied, difference is generated between a time when data is captured in accordance with the synchronous clock and the rising edge of the reception data. As a result, errors upon capturing the reception data are increased.
In order to resolve such a problem, for example, Japanese Laid-Open Patent Application No. 2004-363833 (Patent Document 1) discloses a reception device capable of readily generating accurate synchronous clocks in a simple structure. Further, Japanese Laid-Open Patent Application No. 2005-192 (Patent Document 2) discloses a data recovery method and a data recovery circuit in which when a frequency of input data is f1 and a frequency of polyphase clocks is f2, f1/f2 bits are extracted averagely from each set of polyphase data and data is restored.
Patent Document 1: Japanese Laid-Open Patent Application No. 2004-363833
Patent Document 2: Japanese Laid-Open Patent Application No. 2005-192
However, the inventions disclosed in Patent Document 1 and Patent Document 2 perform synchronization through comparison of an input signal with the edge of one side of the synchronous clock. Thus, the inventions pose problems as mentioned above in that reception characteristics are degraded when the duty cycle of the input signal is varied.